DC-MHS (Datacenter Modular Hardware System) is an Open Compute Project effort that breaks a server into standard modules, so that a host processor module can be mated with different power, storage, network and management parts. M-XIO is its PCIe port. It defines how a host processor module reaches risers, backplanes and add-in devices, mostly over cables.
In short:
- DC-MHS is a set of OCP specifications for modular servers, not a single connector.
- M-XIO defines the PCIe port on the host processor module (HPM), including pinouts and sideband signals.
- M-XIO does not mandate one connector. It sets minimum requirements, and MCIO-based connectors are the common choice.
- Cabled connections are required on every M-XIO port. Direct riser connections are optional.
What DC-MHS Is
A traditional server is designed as one block: motherboard, power, drive bays and network card are chosen together. DC-MHS standardizes the interfaces between those parts so a system builder can change one without redesigning the rest. It is an Open Compute Project sub-project aimed at modular, scalable and pluggable designs. For background on OCP itself, see What is an OCP server?
Several workstreams make up DC-MHS. The ones that matter for connectors are:
- M-XIO (with PESTI): the connector, pinouts and signal interface from the host processor module to PCIe risers, backplanes and devices.
- M-PIC: how the host processor module connects to platform and chassis infrastructure such as cooling, power distribution and networking.
- M-CRPS: requirements for an internal redundant power supply. See our CRPS connector guide.
- M-SIF: shared infrastructure enclosures holding several serviceable modules, with blind-mating and hot-plugging.
DC-MHS sits alongside related OCP specifications such as OCP NIC 3.0 and the DC-SCM management module.
What M-XIO Defines
The M-XIO port is the connector on the host processor module, which acts as the PCIe source. A port can feed an adaptor such as a paddle card, or a carrier or module such as a riser or an EDSFF backplane.
Key points from the specification:
- Lane count: a port has at least four PCIe lanes, with link subdivision down to x1. More lanes are optional. A x4 port carries baseline sideband signals only, and a x8 port adds extended sidebands.
- x16 ports: a x16 port can duplicate sidebands between its lower and upper x8 halves so that it can split into two x8 links going to different destinations.
- PESTI: the PCIe sideband tunneling interface carries sideband signals as virtual wires over one bidirectional line (CBL_PRES_PESTI_N), which keeps the pin count down. If PESTI is not implemented, the cable side pulls that line low.
- Generation neutral: the specification does not name a PCIe generation. Connector and cable must support the speed you intend to train at. If one element cannot, the link trains down.
- Cable requirement: the spec asks for support of 30 AWG or larger twin-ax dual-drain cable.
Which Connectors M-XIO Allows
The M-XIO base specification lists pinouts instead of picking one part. The pinouts it covers are:
- SFF-TA-1016 (MCIO): x4 (38-pin), x8 (74-pin) and x16 (148-pin). A 124-pin option is listed as not recommended.
- SFF-TA-1033: x16, with lower and upper x8 halves.
- SFF-TA-1026: 72-pin, x8 lanes.
Suppliers sell M-XIO products built on these. One example is a combination connector based on MCIO with a 0.6 mm pitch: x8 plus power (90 positions) and x16 plus power (164 positions) versions exist, alongside power-only (16 positions). The x16 plus power version combines two 74-pin signal groups, 12 sideband pins and 4 power pins. Quoted power ratings are 21 A (252 W) as standard, with higher versions at 34 A and 55 A. The same supplier states Gen 5 operation at 32 GT/s with a path to Gen 6 at 64 GT/s. Treat those as supplier figures and confirm against the part's drawing.
Where Cabled PCIe Is Used
M-XIO is meant to link the host processor module to many device types, which the specification gives as illustrative uses:
- PCIe CEM add-in cards, through a cabled riser. See our CEM slot guide.
- OCP NIC 3.0 network cards, including the 4C+ variant.
- EDSFF drives (E1 and E3), directly or through backplanes with or without PCIe switches. See our EDSFF guide.
- Storage class memory devices such as CXL modules at x16, x8 or x4.
- Inline host bus adapters and RAID controllers.
Cabling lets the same host processor module reach different chassis layouts. A direct board-to-board riser fixes where the card sits. A cable lets the card sit wherever the chassis needs it, and the cable can be swapped for another configuration.
Selection Checklist
Ask these questions before you choose an M-XIO connector or cable assembly:
- Which pinout? MCIO x4, x8 or x16, SFF-TA-1033 or SFF-TA-1026. They are not interchangeable.
- What PCIe speed will run over it? Ask for the supplier's tested speed for the full channel, cable length included. The specification is generation neutral, so the datasheet has to prove it.
- Sideband support. Check whether the cable carries the extended sideband set for x8 and x16, and whether PESTI is implemented.
- Power on the same connector? Combo parts carry power pins. Check current per pin and the temperature rise at your load.
- Cable gauge and length. The specification asks for 30 AWG or larger twin-ax. Longer runs cost insertion loss.
- Plug orientation. Straight, reverse straight, right angle and reverse right angle versions exist. Orientation affects cable routing and airflow.
- Mating cycles and latching. Cabled ports in field-serviceable modules get unplugged. Check the rated cycles.
Frequently Asked Questions
What does DC-MHS stand for? Datacenter Modular Hardware System. It is an OCP sub-project for modular server design.
What is the difference between M-XIO and MCIO? MCIO (SFF-TA-1016) is a connector standard. M-XIO is the DC-MHS port specification, which defines pinouts and sideband signals and allows MCIO among other connectors.
Is M-XIO limited to one PCIe generation? No. The specification is generation neutral, so the supported speed depends on the connector, cable and board design.
Does M-XIO require cables? Cabled connections are required for all ports. Direct riser connections are optional.
Is M-XIO the same as OCP NIC 3.0? No. OCP NIC 3.0 is the network card form factor. M-XIO can be used to connect to one.
Where to Go Next
- OCP and ORv3 connectors hub: all OCP connector guides.
- OCP NIC 3.0 guide: network card form factors.
- EDSFF connectors: E1.S and E3.S drive interfaces.
- ORv3 connector compliance checklist: what to ask a supplier.
Sources
- OCP M-XIO base specification r1 v1.04 RC1: port definition, pinouts, lane rules, PESTI, cable requirement.
- Molex DC-MHS overview: workstreams and related standards.
- TE Connectivity M-XIO brochure: combination connector configurations, plug styles and supplier ratings.