Inside a modular server, PCIe links increasingly leave the motherboard on cables instead of running as long board traces. The Open Compute Project's Data Center Modular Hardware System (DC-MHS) standardizes how modular host boards, risers, network cards and storage connect, and its M-XIO interface is the part that carries high-speed PCIe I/O. AMD says its Helion rack follows OCP specifications, which makes DC-MHS part of the 2026 OCP conversation.
This article summarizes what connector vendors publish about M-XIO, notes where their descriptions differ, and lists what is not public yet.
In short:
- TE describes M-XIO connectors as built to the OCP DC-MHS M-XIO base specification and SNIA SFF-TA-1033, and as "based on MCIO connectors".
- TE's published figures include 0.6 mm pitch, 85 ohm impedance, 32 GT/s PCIe Gen5 performance, and power ratings of 21 A to 55 A.
- Molex describes the M-XIO connector differently, as its NearStack PCIe system, so check which connector family a specification revision names before you design around either.
What TE Says M-XIO Connectors Are
TE's M-XIO brochure describes a hybrid connector for both card-edge PCB and cable use that carries high-speed signal and power together:
- Standards: built to the SNIA SFF-TA-1033 specification and the OCP DC-MHS M-XIO base specification, and described as based on MCIO connectors, which the brochure calls the standard internal cabling for PCIe Gen5 and Gen6.
- Configurations: a 16-position power-only version, a 90-position version for x8 plus power, and a 164-position version for x16 plus power.
- Pin structure (x16 plus power): two sets of 74 MCIO-type pins, 12 sideband pins and 4 power pins.
- Signal: 0.6 mm contact pitch, surface-mount, 85 ohm impedance, and 32 GT/s NRZ (PCIe Gen5) performance with a stated path to PCIe Gen6 at 64 GT/s PAM4.
- Power: 21 A (252 W) as standard, and 34 A (408 W) or 55 A (660 W) in a high-power version.
- Cable assemblies: straight and right-angle cable plugs in all three position counts, plus assemblies that adapt to CEM (164 positions), EDSFF (90 positions) and OCP NIC 3.0 (164 positions), and a power cable assembly. Listed lengths are 0.5 m and 1 m.
What Molex Says About DC-MHS Connectors
Molex's DC-MHS page maps several DC-MHS interfaces to connector families:
- M-XIO/PESTI: the NearStack PCIe connector system, described as specified in OCP documentation as the standard connector for PCIe Gen5 at 32 Gbps, and meeting SFF-TA-1026.
- M-PIC: the KickStart connector system, plus Micro-Fit+ and Pico-Clasp connectors. KickStart is recommended for cable-optimized boot-peripheral connections and meets SFF-TA-1036.
- M-SIF: Impel and Impel Plus backplane connectors, with Impel Enhanced designed for PCIe Gen6 channel requirements.
- NIC 3.0: QSFP-DD and Sliver Edge card connectors, aligned with SFF-TA-1002. DC-SCM: Sliver Edge card connectors.
- M-CRPS: no connector is named. Our guide to CRPS power supply connectors covers that interface.
Where the two vendors differ: TE ties M-XIO to MCIO-based connectors and SFF-TA-1033, while Molex ties M-XIO to NearStack and SFF-TA-1026. We have not reviewed the text of the OCP M-XIO base specification, so we cannot say which connectors it names, and the two may simply be different vendor implementations of the same role. Check the revision of the specification you are designing to.
What Has Not Been Published
- Electrical limits: TE's brochure gives no voltage, per-pin current, temperature range, mating cycles, insertion loss or crosstalk figures.
- Gen6 status: PCIe Gen6 is described as a path, not as a certified capability.
- x4 support: it is not mentioned in the brochure.
- Helion: AMD has not published which connectors Helion uses.
Our Analysis: What It Means for Connector Selection
The points below are our engineering assessment, not vendor data.
1. The power ratings point to a 12 V supply
Dividing each published wattage by its current gives 252 W ÷ 21 A = 12 V, 408 W ÷ 34 A = 12 V and 660 W ÷ 55 A = 12 V. That suggests the ratings assume a 12 V supply, but TE's brochure does not state the voltage, so confirm it with the supplier. It is also a reminder to check the current rating at your operating temperature, not only the headline figure.
2. Gen5 and Gen6 have the same Nyquist frequency
PCIe Gen5 sends 32 GT/s with NRZ, which puts the Nyquist frequency at 16 GHz. PCIe Gen6 sends 64 GT/s with PAM4, which is 32 gigabaud, and the Nyquist frequency is again 16 GHz. The connector's bandwidth requirement therefore stays similar, but PAM4 has three eyes instead of one and leaves much less margin for reflections and crosstalk. A connector that is acceptable at Gen5 can fail at Gen6 because of return loss and crosstalk, not bandwidth. Our guides to PAM4 eye diagrams and PCIe Gen5 and Gen6 interconnects cover this in more detail.
3. Why cables replace long board traces
A cable assembly generally loses less signal per unit length than a printed circuit board trace, which is why designers move high-speed links onto cables at these speeds. An 85 ohm cable also matches the nominal differential impedance of a PCIe link, and lengths such as 0.5 m and 1 m show the reach TE lists today.
4. Adapters into existing connector families
Because TE offers M-XIO cable assemblies that adapt to CEM, EDSFF and OCP NIC 3.0, one cable family can bridge a modular host board to several existing form factors. For those endpoints, see our guides to EDSFF connectors, NIC 3.0 and modular hardware interconnects and CEM slots.
5. Questions to ask a supplier
- Which revision of the OCP M-XIO base specification does the part conform to, and which SFF-TA specification does it meet?
- What are the rated current per contact and the temperature derating curve?
- What are the measured insertion loss and crosstalk through the full cable assembly, and at which PCIe generation?
- Is the part validated for PCIe Gen6, or only for Gen5 with a path to Gen6?
- How many mating cycles is it rated for, and how does contact resistance change over those cycles?
For the compute blade that is expected to use this kind of modular interface, see AMD Helion: what it means for connectors. For another rack that moves cooling and power to blind-mate interfaces, see NVIDIA MGX 1.2. For management modules in the same family, see our DC-SCM connector guide. More coverage is in our OCP server interconnects hub.
Last updated October 15, 2026. We will update this article when the full DC-MHS M-XIO specification and supplier test data are available.