AMD has announced Helion, a rack-scale reference architecture built for agentic AI workloads. Most coverage of the announcement focuses on software orchestration and headline CPU core counts. Hardware engineers care about something else: the mechanical, thermal and electrical interconnect realities of packing this much compute into an open rack.
This article separates the confirmed hardware facts from our own engineering analysis of what they mean for connectors and 48V power delivery, and it notes where designers must wait for the full Open Compute Project (OCP) specification.
In short:
- Helion comes as a CPU-only rack (up to 32,768 "Zen 6" cores) and a mixed CPU and GPU rack, in air-cooled or liquid-cooled versions.
- AMD has not yet published rack power, power shelf, busbar or connector details.
- Even so, the confirmed CPU power levels point to heavy demands on busbar contacts, liquid-cooling couplings and high-speed cabling.
Confirmed Specifications and System Details
Two configurations. Helion is a modular rack-scale design:
- Hyperscale CPU-only: built for agent execution, memory routing and tool orchestration, with up to 32,768 "Zen 6" cores using 6th Gen AMD EPYC ("Venice") processors. That is equivalent to 128 sockets of 256-core processors.
- Enterprise mixed: pairs EPYC CPU blades with accelerator blades using AMD Instinct MI350P GPUs, for local inference and agent execution in one rack.
CPU node profiles. AMD outlined several node types for different workloads:
- Dense: a ~400 W TDP processor.
- Balanced: 256 cores per socket at ~600 W TDP.
- High-frequency: 96 cores per socket, clocked up to about 5 GHz, for latency-sensitive agent logic.
Networking. Up to 102 Tbps of aggregate rack networking bandwidth.
Form factor and OCP alignment. Helion is reported to be built on the 21-inch Open Rack v3 (ORv3) frame, and AMD says it follows an OCP specification. The OCP specifications most relevant to a rack of this kind, and referenced in this analysis, are:
- ORv3: the open rack frame and power delivery architecture.
- DC-MHS: Data Center Modular Hardware System, for modular CPU compute blades.
- DC-SCM: Data Center Secure Control Module, for out-of-band management.
- HPR: High Power Rack guidelines for higher-power racks.
- OCP NIC 3.0: standardized network mezzanine card interfaces.
- Caliptra: the open-source silicon root of trust.
Cooling. Available as direct liquid cooling (DLC) or air cooling.
OCP plan. AMD intends to contribute the full Helion specification to OCP. Formal contribution and committee review were still pending at the time of writing.
Partners and availability. Integration partners include Cisco, Dell, HPE, Supermicro and Wiwynn, among others. Initial partner systems are due to ship in November 2026.
What AMD Hasn't Disclosed Yet
Compute and fabric headlines are public, but the granular power and interconnect figures are not:
- Peak rack power: the total nameplate power of a fully populated rack has not been declared.
- Power shelf configuration: rectifier module counts, N+1 or N+N redundancy options and power shelf slot allocation are unconfirmed.
- Connector part numbers: board-to-board connectors, blind-mate busbar clips and cabled backplane parts are TBD until the specification is published.
- PCIe generation and NIC details: not yet announced.
Our Analysis: ORv3 Connectors and Power Delivery
The analysis below is our engineering assessment, built on established ORv3-class design practice. It is not connector data published by AMD.
Illustrative ORv3-class power and cooling path
(not AMD's published design)
+-------------------------------------------------------+
| ORv3 Power Shelf |
| [ 48V AC/DC Rectifiers ] [ Shelf Controller ] |
+---------------------------+---------------------------+
|
| (blind-mate power clip)
v
+-------------------------------------------------------+
| Vertical 48V DC Busbar |
+-----+------------------------+------------------+-----+
| | |
| (blind-mate power) | (blind-mate) | (blind-mate)
v v v
+--------------+ +--------------+ +--------------+
| CPU Blade 1 | | CPU Blade 2 | | GPU Blade 1 |
| (Venice EPYC)| | (Venice EPYC)| | (Instinct) |
+--------------+ +--------------+ +--------------+
^ ^ ^
| (blind-mate QD) | (blind-mate QD) | (blind-mate QD)
+-----+------------------------+------------------+-----+
| Liquid-Cooling Manifold (DLC) |
+-------------------------------------------------------+1. Power distribution: 48V busbar and blind-mate clips
Even without a published rack rating, the arithmetic is straightforward. In the CPU-only configuration, assuming 256-core sockets throughout:
128 sockets × 400–600 W = 51.2–76.8 kW for the processors alone.
Memory, network switches, optics and any local GPUs add to that, so total rack power plausibly lands around 80 kW or more. If a single 48V busbar carried 80 kW, that is roughly 1,670 A. AMD has not said how Helion distributes power, so treat this as an illustration of scale, not a design figure. At this level, designers may split the load across several power zones or look at higher-voltage distribution.
What this means for the connector:
- Contact resistance: blind-mate power clips must stay at very low resistance, typically well under 1 mΩ per contact, under continuous thermal load. Heating scales with current squared, so small resistance differences become real watts.
- Alignment and durability: blades slide onto the copper busbar through rear-mounted clips. The clips must absorb cumulative chassis tolerance during blind insertion and keep their normal force across repeated service cycles.
2. Aligning electrical and liquid blind-mate interfaces in DLC racks
In liquid-cooled versions, direct-to-chip cold plates on 600 W CPUs and high-power GPUs add a second blind-mate problem. Each blade must engage two systems at the rear at the same moment:
- the electrical 48V busbar power clip, and
- the drip-free quick-disconnect (QD) couplings on the liquid-cooling manifold.
Busbar contacts and fluid couplings have different insertion forces and compliance tolerances. Designers typically rely on alignment guide pins, floating connector shrouds and PCB strain relief so that insertion forces do not crack solder joints.
3. High-speed board-to-board and near-chip cabling
AMD has not announced Helion's PCIe generation. For context, if a platform like this uses PCIe Gen7 (128 GT/s with PAM4), the Nyquist frequency is 32 GHz. At that frequency, long PCB traces can exhaust the insertion loss budget, and designers commonly move high-speed signals onto near-chip twinax cable assemblies that route to rear I/O or OCP NIC 3.0 slots. Our PCIe Gen7 connector guide covers those loss budgets in detail.
Up to 102 Tbps of rack networking also implies dense high-speed cabling and connectors, whichever PCIe generation Helion uses.
On the management side, DC-MHS and DC-SCM define standardized modular interfaces for compute blades and management modules. See our DC-SCM connector interface guide for the connector details. For the cabled PCIe interface in the same DC-MHS family, see our M-XIO and MCIO connector guide. Caliptra is a silicon-level security feature, so it shapes the security architecture rather than the connector choice.
For the busbar and power connectors used in ORv3 racks, see our guide to Open Rack busbar power connectors our UQD and UQDB quick disconnect guide, and our OCP server interconnects hub.
Last updated October 14, 2026. We will update this article after AMD publishes the Helion specification to OCP and partner systems ship in November 2026.